Subhro Ghosal*, Madhabi Ganguly and Debarati Ghosh Pages 433 - 446 ( 14 )
Background: The stringent technological constraints imposed by the requirement of ultra-sharp doping profiles associated with the sub-30 nm regime has led to the search for alternatives to the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET). An obvious alternative is a device whose architecture does not have any junctions in the sourcechannel- drain path. One such device is the Junctionless transistor comprising of an isolated ultrathin highly doped semiconductor layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. For widespread application in today’s high-speed circuits, a key factor would be its effectiveness as a switch.
Methods: In this work we have studied the relative sensitivity of two such parameters namely the ION/IOFF ratio and gate capacitance to variations in several structural parameters of the device namely channel width, composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region and non-uniformity in the doping profile.
Results: The work demonstrates through device simulations that replacement of Si with Si-Ge leads to an improvement in the performance.
Conclusion: The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.
JLT, ON/OFF ratio, dv/dt turn on, gate capacitance Si-Ge, variability, RDD.
Department of Electronic Science, APC College, Kolkata, Department of Electronics, West Bengal State University, Kolkata, Department of Basic Sciences and Humanities, RERF, Kolkata